verification
1 statements across 1 episodes · 0 bullish · 0 bearish · 1 people on the record · first statement Sep 3, 2026 by Rene Haas · across every show →
Everything said about verification, oldest first
Sep 3, 2026 neutral
Haas: Verification and validation take more time in chip design than RTL
“Chip design can take anywhere from 24 to 36 months, depending on the complexity of the chip, et cetera. The actual design of the architecture, the RTL generation, if you will, the mapping of the architecture, Is not the largest amount of time. The largest amou…”