Assertion Contradicted AI assessment confidence: 90% certainty 3/5 debate potential 1/5

Haneke: ASIC verification takes 3 to 4 times more resources than design

RJ Haneke · Scaling Past Informal AI - Carina Hong, Axiom Math · Jun 3, 2026 · at 47:52

Host RJ Haneke notes the standard industry resource split between chip design and verification during a discussion with Axiom Math CEO Carina Hong.

0:00 / 0:09exact quote · 9.4s

▶ Watch the full episode on YouTube → 720p mp4 · rendered on demand · StarZero watermark

“My understanding is that the industry standard for design to verification in ASIC ASIC project is like one to three, one to four.”

quote is from the automated transcript, cleaned for reading: filler sounds and stutters are removed, nothing is rephrased. names can be misheard (the analysis reads context, assessments check outside sources). how →

The claim, plainly

The industry standard ratio of design to verification in an ASIC project is approximately 1:3 to 1:4.

a quote alone can be ambiguous, so this restates it with the references and context of the conversation around it resolved. AI-written; the tape below the player is the source.

Assessment

Published semiconductor industry benchmarks do not corroborate that the general industry standard design-to-verification ratio is 1:3 to 1:4. According to the long-running Wilson Research Group / Siemens EDA Functional Verification Studies (covering 2012–2024), the industry-wide mean peak headcount ratio of ASIC design engineers to verification engineers is approximately 1:1, and verification accounts for roughly 53% to 57% of total IC/ASIC project time (an effort ratio of ~1:1 to 1:1.3). While ratios of 1:3 to 1:5 occur in specialized, high-complexity subsegments (such as CPU/processor cores and select safety-critical IP blocks), they do not represent the overall industry standard for ASIC projects.

Wilson Research Group / Siemens EDA Functional Verification Trend Reports (2020–2024) establish that the industry-wide mean peak headcount ratio for IC/ASIC design to verification is approximately 1:1.
The same studies measure total IC/ASIC project time spent in verification consistently at 53%–57%, corresponding to an effort ratio of ~1:1 to 1:1.3 rather than 1:3 or 1:4.
Higher verification ratios of 1:3 to 1:5 are observed only in specialized subsegments, such as complex processor cores and high-complexity IP blocks, rather than across standard ASIC projects.

Checked against

[1] semiwiki.com [2] scribd.com [3] semiengineering.com [4] siemens.com [5] benharoosh.co.il [6] tessolve.com [7] siemens.com [8] dvcon-proceedings.org

"Wilson Research Group" "percentage of project time spent in verification" "Wilson Research Group" "mean peak number of engineers" IC ASIC Wilson Research Group Functional Verification Study design verification ratio ratio of design engineers to verification engineers ASIC industry benchmark ASIC design to verification effort ratio 1 3 1 4

assessed as of 2026-09-02

This assessment is an AI reading of a public statement, made against the cited references with the confidence shown. It can be wrong. The quote, the tape and the references are all on this page; if something is off, use report an error below. full disclaimer →

Mentioned

ASIC design verification

⚑ Spot an error? Report it

More from RJ Haneke

Insight

Haneke: Lab Experimentation Differentiates AI for Science From B2B SaaS

“One of the themes that has run through the podcast is how the lab and experimentation and the real world have probably the biggest impact and have the most relevance to whether something is AI for science or something like B to B SAS.”

RJ Haneke Jul 21, 2026 ▶ 0:53 🔬Causal Models Need Causal Data - Xaira’s X-Cell model (Bo Wang & Ci Chu)

Haneke: ASIC verification takes 3 to 4 times more resources than design

More from RJ Haneke

Turn any episode into a week of clips.