Jenik: Traditional chip design loses performance by separating digital logic and physics
Benedikt Jenik · Faster Chips That Don't Melt — Anima Anandkumar & Benedikt Jenik, Accelerated Understanding · Sep 4, 2026 · at 21:05
Benedikt Jenik of Accelerated Understanding explains the limitations of conventional chip design pipelines compared to physics-informed co-design.
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“Especially when you look at the chip design itself, it was much more a, let's start in the digital, let's freeze the digital in, let's send it through some physics for a one time check, like the PDK dictates, I have to have The following feature, otherwise TSNC doesn't make it for you. And it stops there. Like, it's like, ooh, do we have enough headroom to push it through? But we're not taking advantage today of that headroom to get extra performance.”
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