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Verilog

1 statements across 1 episodes · 0 bullish · 0 bearish · 1 people on the record · first statement Feb 26, 2026 by Reiner Pope · said 9 times in 1 episodes since 2026 · across every show →

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Feb 26, 2026 neutral
Assertion Not checkable as stated
Pope: AI labs apply RL to software code, not chip architecture
“Models are extremely good at Rust and Python. They've done a lot of RL on them. They have not done as much RL on Verilog. They've done almost none on, okay, write, write me a markdown file that describes a chip architecture.”
Reiner Pope Feb 26, 2026 ▶ 45:39 Reiner Pope of MatX on accelerating AI with transformer-optimized chips
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