Smulyanski: On-die SRAM accelerators excel at LLM decode due to high bandwidth
Misha Smulyanski · Multi-GPU Kernels, Intelligence per Watt, Heterogeneous Inference, and More | YC Paper Club · Y Combinator · Jul 29, 2026 · at 55:29
Misha Smulyanski discusses AI hardware architectures at YC Paper Club, explaining how on-die SRAM accelerators bypass the HBM memory bandwidth bottleneck during LLM decode phases.
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“The SRA machine basically keeps the entire weight matrix in SRA memory on DAI, so the, you got a lot more bandwidth, right, because it's on chip, right, so you can access, you know bytes over cycles, right, the chip interconnect is also fast, you can go, like between different units in a couple of cycles, right, so everything is kind of kept on DAI, and so they're very efficient, right, so I call them GMV, like, Matrix Vector Multiplication Accelerators, right, which just happens to be, like, really good, ah, for a decode, because the code is very, very, ah, bandwidth-bound. They offer you, like, significantly more, ah, bandwidths, ah, right, and, ah, significantly, ah, lower latency”
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